1. Field of the Invention
The present invention relates to computer-aided design tools for electrical circuits, and more particularly to a system for placing gates at specific locations in a circuit design based upon drive strengths and wireloads of the gates.
2. Related Art
Circuit design is presently accomplished primarily through the use of computer aided design (CAD) tools, which take as input a circuit specification and automatically generate circuit descriptions suitable for implementation. Circuits are initially specified in a hardware description language, such as VHDL or Verilog. The VHDL standard is codified in Institute for Electrical and Electronic Engineers (IEEE) standard 1076-1993, and the Verilog standard is codified in IEEE standard 1364-1995.
A hardware description language (HDL) specification of a circuit typically includes a set of equations that specify how the circuit behaves functionally. These equations are "synthesized" into a gate-level implementation of the circuit, which specifies what logic gates are used to implement the circuit as well as the interconnections between the logic gates. After the circuit is synthesized into a gate-level implementation, the system typically performs a "placement" operation to place gates at specific locations on a semiconductor die. Next, the system performs a "routing" operation to route the interconnections between the gates. Note that the "routing" operation is presently becoming less of a performance impediment than the "placement" operation, because modern circuit technologies provide multiple signal layers. This makes it easier to route interconnections and makes it possible to create "feed throughs," to pass signal lines through other gates, instead of around them.
As new semiconductor processing technologies push geometries below 0.5 microns, circuit timing is beginning to be dominated by wireload and wire delay instead of gate delay. This change has significant implications for the optimizations currently performed by existing CAD tools.
Existing CAD systems typically perform placement in one of two ways. (1) Timing-based placement iteratively simulates timing for the circuit and adjusts the placement to meet timing requirements. This tends to produce a good placement. However, the timing simulations can run for days or weeks, which can be an unacceptably long time. (1) Connectivity-based placement considers the number of connections to a gate. For example, if a gate has three input lines and a single output line, a connectivity-based placement scheme gives the three input lines a greater weight than the single output line in deciding where to place the gate. This tends to pull the gate toward the three input lines, thus shortening the three input lines and lengthening the output line. Connectivity-based placement requires significantly less computational time than timing-based placement. However, it tends to produce a less optimal placement. Furthermore, connectivity-based placement will become less accurate as wireloads begin to dominate timing delays. What becomes more significant is the wireload on a signal line and the drive strength of a gate that is driving the signal line.
What is needed is a CAD system that takes into account gate drive strengths and/or wireloads in placing gates at specific locations in a semiconductor chip design.